Various microprocessing techniques have been studied and developed to enhance packaging density in the field of very large scale integrated circuits, and a design rule has already reached a sub-half micron order. One of techniques which can satisfy these tight microprocessing requirements is a CMP technique. This technique can perform microporocessing in a production process of semiconductor devices by completely flattening a layer to be exposed to light, and thereby can improve a product yield. Therefore, the CMP is a technique needed for flattening inter layer dielectrics, achieving shallow trench isolation, or the like.
A local oxidation method of silicon (LOCOS) has heretofore been used for isolation in an integrated circuit. More recently, however, it has been replaced with a shallow trench isolation method to decrease an isolation width. The CMP is an essential technique for the shallow trench isolation method to remove a surplus silicon oxide film formed on a wafer substrate. In order to stop polishing, a silicon nitride film is usually formed as a stopper under the silicon oxide film.
In a semiconductor device production process, an alkaline (pH: higher than 9) polishing slurry of fumed silica particles has been widely used for the CMP to flatten an insulating film of silicon oxide or the like produced by plasma CVD (chemical vapor deposition), low-pressure CVD or the like. However, a polishing slurry of silica which keeps alkaline to increase a rate of polishing a silicon oxide film polishes a silicon nitride film as a stopper also at a high rate, thereby causing problems, e.g., difficulty in uniformly polishing the wafer over the entire surface thereof (i.e., difficulty in flattening to a high extent) or occurrence of many polish scratches which can adversely affect electrical characteristics.
Recently, a polishing slurry of cerium oxide (disclosed by, e.g., Japanese Patent Laid-open Publication No. 5-326469) has been widely used as a polishing slurry for polishing glass surfaces, e.g., photomask and lens surfaces. The cerium oxide polishing slurry has advantages, i.e., polish of an silicon oxide film at a higher rate and occurrence of a relatively small number of polish scratches, as compared with a silica polishing slurry. Therefore, application of the cerium oxide polishing slurries to polishing semiconductors has been studied recently, and some of the polishing slurries have been already commercialized (e.g., Japanese Patent Laid-open Publication No. 9-270402).
However, there has not yet been developed a cerium oxide polishing slurry capable of completely flattening the entire surface of a wafer substrate on which various devices are assembled substantially without causing the polish scratches which may deteriorate electrical characteristics.
It is an object of the present invention to provide a CMP polishing slurry capable of flattening a surface to a high extent, substantially without causing polish scratches which may deteriorate electrical characteristics. It is another object of the present invention to provide a polishing method which uses the same polishing slurry.